This invention is related to the field of dual damascene semiconductor processing in general and more particularly to a method and mask for line first dual damascene processing.
An important part of the fabrication of very large scale integrated circuits is the formation of vias and other conductive interconnections between the various circuit elements. In the line first damascene process, the substrate surface, including transistors and other devices formed on the wafer, is first covered with a dielectric layer such as oxide. A patterned photoresist profile is then formed on the surface of the dielectric. The resist profile has openings, or holes, in the photoresist corresponding to the areas where interconnect lines are to be formed in the dielectric. Other areas of the resist are formed into openings to create vias. The areas where the lines and vias overlap are also openings. The photoresist-covered dielectric layer is then etched to remove oxide underlying the opening in the photoresist which form the lines. A second etch using a second mask to remove the oxide remaining between the bottom of the lines and the layer below to create the vias. The photoresist is then stripped away.
Production of integrated circuits using the damascene process involves high-resolution photolithography to create ultra-thin lines and vias in the dielectric. Patterns of openings are formed in the overlying positive photosensitive resist (hereinafter xe2x80x9cphotoresistxe2x80x9d or xe2x80x9cresistxe2x80x9d) by directing the desired patterns of light onto the photoresist, the light being of a wavelength to which the photoresist is sensitive. Subsequently, the photoresist is xe2x80x9cdevelopedxe2x80x9d to remove the light-exposed areas, leaving behind a photoresist mask on the surface of the dielectric. The photoresist mask is then used as a pattern in subsequent etching of the underlying dielectric. A similar process giving a mirror effect occurs when using a negative photoresist. Examples of a mask for the lines, 100, and the mask for the vias, 105 in a line first patterning are shown in FIG. 5a and 5b, respectively. Notice that the areas where the lines and vias overlap, 110, in FIG. 5a, shown as dotted lines, are openings on both masks. For convenience in the claims, the areas where the lines and vias overlap will be referred to as the intersection of a set of lines and a set of vias, since the intersection of two sets is the overlap between them. In this example for the masks for a via first patterning are substantially the same as the masks for the line first patterning and are shown in FIG. 4 with the lines, 100, vias, 105, and overlaps, 110, represented similarly.
As devices on semiconductor wafers shrink to sub-micron dimensions and the number of individual components on a chip necessitate ever higher packing densities, the architectural complexity of interconnections continues to grow. The photoresist that is patterned and etched to form the lines can be deposited in the openings created and introduce a variable that is difficult to control when forming the vias in a second etch. Residual photoresist in the bottom of the opening that forms the lines can create an uneven surface that is difficult to focus on. If focus is not accurate then the second formed vias might not have the defined shape sought.
Thus, there remains a need for a method and apparatus for producing optimally shaped lines and vias using dual damascene technology.
It is therefore an object of the present invention to provide a method for forming lines exclusive of vias using dual damascene technology.
It is a further object of the present invention to provide a mask capable of forming lines exclusive of vias using dual damascene technology.
In accordance with the above listed and other objects, we provide a method of forming a dual damascene pattern, comprising the steps of:
a) Depositing a layer of a first non-conductive material;
b) Depositing a layer of photoresist on the first layer of the non-conductive material;
c) Exposing the layer of photoresist to a first mask, the first mask defining a first mask pattern of lines and vias, the first mask pattern having two portions, a first portion of the first mask defining the lines and a second portion of the first mask defining the vias, wherein only the first portion of the first mask pattern is transferrable to the photoresist;
d) Etching the layer of first non-conductive material according to the pattern transferred to the photoresist by first mask in step c;
e) Exposing the layer of photoresist to a second mask, the second mask defining a pattern of vias, the second mask pattern having a first portion of the second mask, the first portion of the second mask defining the vias, wherein the first portion of the second mask pattern is transferrable to the photoresist;
f) Etching the layer of first non-conductive material to the pattern transferred to the photoresist in step e.